Chip manufacturers continue to vie for every spare nanometer of space to keep shrinking circuit sizes, but over the next five years, a technology involving much larger dimensions (hundreds or thousands of nanometers) could be equally important.
This technology, known as hybrid bonding, stacks two or more chips within the same package. This allows chip manufacturers to increase the number of transistors in their processors and memory, even as the miniaturization of transistors is generally slowing down, which once propelled Moore's Law. In May of this year at the IEEE Electronic Components and Technology Conference (ECTC) held in Denver, research teams from around the world announced several improvements to the technology, some of which could lead to a record level of connection density between 3D stacked chips: about 7 million connections per square millimeter of silicon.
Yi Shi of Intel told engineers at the ECTC conference that all these connections are necessary due to the new characteristics of semiconductor progress. Moore's Law is now subject to a concept called System Technology Co-optimization (STCO), according to which the functions of a chip (such as high-speed cache memory, input/output, and logic) will be manufactured separately using the manufacturing technology most suitable for each function. These subsystems are then assembled using hybrid bonding technology and other advanced packaging technologies, allowing them to function as a single silicon wafer. However, this can only be achieved with high-density connections.
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Among all advanced packaging technologies, hybrid bonding offers the highest vertical connection density. Therefore, it is the fastest-growing area in the advanced packaging industry, says Gabriella Pereira, a technology and market analyst at Yole Group. According to Yole Group's forecast, by 2029, the entire market size will more than triple, reaching $38 billion, at which time hybrid bonding technology will account for about half of the entire market, although it is currently only a small part.
In hybrid bonding, each chip's top surface has copper pads. Surrounding the copper is an insulating layer, usually silicon dioxide, and the pads themselves are slightly recessed from the surface of the insulating layer. After chemically modifying the oxide, the two chips are pressed face to face, aligning the recessed pads on each chip. The sandwich is then slowly heated, firmly connecting the oxides and expanding the copper to form electrical connections.
1. Hybrid bonding begins with two wafers or a chip and a wafer facing each other. The mating surfaces are covered with an oxide insulating layer and slightly recessed copper pads connected to the chip's interconnect layer.
2. The silicon wafers are pressed together to form an initial bond between the oxides.
3. The stacked silicon wafers are then slowly heated to firmly connect the oxides and expand the copper to form electrical connections.In order to form stronger bonds, engineers are flattening the last few nanometers of the oxide. Even slight bumps or warps can disrupt the tight connection. Copper must be recessed from the oxide surface to just the right degree. Too much recess and no connection can be formed. Too little recess and it will push the wafer away. Researchers are studying how to control the copper to a single atomic layer horizontally. The initial connection between the wafers is a weak hydrogen bond. After annealing, the connection becomes a strong covalent bond. Researchers expect that using different types of surfaces (such as silicon carbide, which has more positions to form chemical bonds) will make the connection between the wafers more robust. The final step of hybrid bonding may take several hours and requires high temperatures. Researchers hope to reduce the temperature and shorten the process time. Although the copper on the two wafers is squeezed together to form an electrical connection, the metal grain boundaries usually do not span from one side to the other. Researchers are trying to make large single-crystal copper grains span the boundaries to improve conductivity and stability.
Hybrid bonding processes can both connect individual-sized chips to wafers filled with larger-sized chips, and connect two wafers filled with the same size chips. Pereira said that the latter process is more mature than the former, partly because of its application in camera chips. For example, engineers at the European microelectronics research institution Imec have created some of the most dense wafer-to-wafer bonding ever, with a bonding distance (or pitch) of only 400 nanometers. However, the chip-to-wafer bonding pitch of Imec is only 2 micrometers.
Compared with the advanced 3D chips currently produced, the latter has made a huge progress, as the latter's connection pitch is about 9 micrometers. Compared with the previous generation of technology, this is a bigger leap: the pitch of the solder "microbumps" is only a few tens of micrometers.
"In terms of existing equipment, the alignment between wafers is easier than the alignment between chips. Jean-Charles Souriau, the head of integration and packaging science at the French research institution CEA Leti, said: "Most microelectronic processes are manufactured for complete wafers. However, in high-end processors of companies such as AMD, the chip-on-wafer (or grain-to-wafer) technology shines, which is used to assemble computing cores and high-speed buffer memory in its advanced CPUs and AI accelerators.
In order to make the pitch of these two schemes smaller and smaller, researchers are working on making the surface flatter, making the bonded wafers stick together better, and shortening the entire process time, reducing its complexity. If this can be achieved, it can completely change the way chips are designed.
Research progress of different methods
The recently conducted wafer-level (WoW) research has achieved the most compact pitch from 360 nanometers to 500 nanometers, where a lot of effort has been put into flatness. To bond two wafers together with an accuracy of 100 nanometers, the entire wafer must be almost completely flat. If there is any curvature or warping, the entire wafer cannot be connected.
Flattening the wafer is a process called chemical mechanical planarization (CMP). It is crucial to chip manufacturing, especially when producing interconnect layers above the transistors.
"Souriau said: "CMP is a key parameter of hybrid bonding that we must control. The results shown at ECTC indicate that CMP has taken another step, which can not only make the entire wafer flat, but also reduce the nano-level roundness on the insulating layer between the copper pads to ensure better connection.
Other researchers are focused on ensuring that these parts are firmly bonded together. To this end, they try to use different surface materials, such as silicon carbide instead of silicon oxide, and adopt different schemes to chemically activate the surface. Initially, when the wafer or chip is pressed together, they are fixed together by relatively weak hydrogen bonds. People are concerned about whether all parts can remain in place during further processing steps. After connection, the wafers and chips will be slowly heated in a process called annealing to form stronger chemical bonds. How strong these chemical bonds are - and even how to find out these chemical bonds - is the subject of most of the research topics at the ECTC conference.The ultimate bond strength partly comes from the copper connections. The annealing step causes the copper to expand in the gap, forming a conductive bridge. Samsung's Seung Ho Hahn explained that controlling the size of the gap is crucial. If the expansion is too small, the copper will not fuse. If the expansion is too large, the wafer will be pushed away. This is a nanometer-scale issue, and Hahn reported his research on a new chemical process, hoping to achieve just the right amount of copper by etching away one atomic layer at a time.
The quality of the connection is also important. The metal in chip interconnects is not a single crystal but is composed of many grains, which are oriented in different directions. Even after the copper expands, the grain boundaries of the metal typically do not span from one side to the other. This spanning should reduce the resistance of the connection and improve its reliability. Researchers from Tohoku University in Japan reported a new metallurgical scheme that could ultimately produce large single-crystal copper that spans the boundaries. "This is a huge change," said Takafumi Fukushima, an associate professor at Tohoku University. "We are now analyzing the reasons behind it."
Other experiments discussed at ECTC focused on simplifying the bonding process. Several experiments attempted to reduce the annealing temperature required for bonding - typically around 300 degrees Celsius - to minimize the risk of damage to the chip due to prolonged heating. Researchers from Applied Materials presented research progress on a method that fundamentally shortens the time required for annealing (from several hours to just 5 minutes).
Currently, Chip-on-Wafer (CoW) hybrid bonding is more useful for advanced CPU and GPU manufacturers: it allows chip manufacturers to stack chips of different sizes and test each chip before binding it to another chip, ensuring that an expensive CPU is not ruined by a single defective part.
However, CoW has all the difficulties of Wafer-on-Wafer (WoW) but with fewer options to alleviate these difficulties. For example, Chemical Mechanical Polishing (CMP) is designed to flatten wafers, not individual grains. Once the chips are cut from the source wafer and tested, it is difficult to improve their bonding readiness.
Nevertheless, researchers from Intel reported CoW hybrid bonding technology with a pitch of 3 microns, as mentioned earlier, and a research team from Imec also successfully achieved a pitch of 2 microns, mainly by making the transferred die very flat while it is still attached to the wafer and maintaining exceptional cleanliness throughout the process. Both teams used plasma etching technology to cut the chips, instead of the conventional method using dedicated blades. Unlike blades, plasma etching does not cause edge chipping, resulting in debris that could affect the connection. It also allows the Imec team to shape the mold, creating chamfers that reduce mechanical stress that could damage the connection.
Several researchers at ECTC said that CoW hybrid bonding is essential for future High Bandwidth Memory (HBM). HBM is DRAM chips stacked on a control logic chip, currently with 8 to 12 chips. HBM is usually placed in the same package as a high-end GPU and is crucial for handling the tsunami-like data volume required to run large language models like ChatGPT. Today, HBM chips are stacked using microbump technology, so there are tiny solder balls surrounded by organic filler between each layer.
But as artificial intelligence demands more memory, DRAM manufacturers hope to stack 20 layers or more in HBM chips. The volume occupied by microbumps means that these stacked layers will soon be too high to be properly packaged with a GPU. Hybrid bonding technology can reduce the height of HBM and also more easily remove excess heat from the package, as there is less thermal resistance between layers.
At ECTC, Samsung engineers demonstrated that hybrid bonding technology can produce a 16-layer HBM stack. "I believe that stacks of more than 20 layers can be manufactured using this technology," said Hyeonmin Lee, a senior engineer at Samsung. Other new CoW technologies also help to introduce hybrid bonding technology to high-bandwidth memory. Researchers at CEA Leti are exploring so-called self-alignment technology, said Souriau. This will help ensure that good CoW connections can be achieved using only chemical processes. Certain parts of each surface will be made hydrophobic, while others will be made hydrophilic, allowing the surfaces to automatically slide into place.
At the ECTC conference, researchers from Tohoku University and Yamaha Robotics reported the results of a similar scheme. They used the surface tension of water to align 5µm pads on DRAM experimental chips with an accuracy of more than 50nm.The Limits of Hybrid Bonding
Researchers are almost certain to continue narrowing the pitch of hybrid bonding connections. TSMC's Pathfinding System Project Manager, Han-Jong Chia, informed engineers at ECTC that a 200-nanometer WoW pitch is not only possible but also ideal. TSMC plans to introduce a technology called backside power delivery within two years. (This technology places the extensive power delivery interconnects beneath the silicon surface instead of above it. According to calculations by TSMC researchers, the top layer can be better connected to smaller hybrid bonding pads due to the absence of these power conduits. The use of 200-nanometer bonding pads with backside power delivery will significantly reduce the capacitance of three-dimensional connections, thereby increasing energy efficiency and signal speed by as much as eight times compared to the use of 400-nanometer bonding pads.
Chia believes that at some point in the future, if the bonding pitch is further reduced, then "folding" circuit blocks to build across two chips may become feasible. In this way, some long connections within the current circuit blocks can be replaced with vertical shortcuts, which may potentially speed up computing and reduce power consumption.
Hybrid bonding may not be limited to silicon. "The development of silicon-silicon wafers is very rapid today, but we are also seeking hybrid bonding between gallium nitride and silicon wafers, glass wafers... all materials," said Souriau from CEA Leti. His organization has even demonstrated hybrid bonding research on quantum computing chips, which involves the arrangement and bonding of superconducting niobium instead of copper.
"It's hard to say what the limit will be. Things are moving very fast," said Souriau.
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