The main players in most Electronic Design Automation (EDA) software are producing more advanced timing convergence tools, which determine the clock frequency of a chip while meeting the design timing constraints.
To maintain a leading position in the era of artificial intelligence, semiconductor companies and even many system companies are launching a new type of super-large-scale System on Chip (SoC), using advanced process nodes to pack hundreds of billions of transistors into silicon chips, breaking through the limits of modern chips. These chips contain more than a billion standard cells, an increasing number of third-party IPs, and up to thousands of clocks to keep everything coordinated. With the continuous shortening of time to market, all these factors lead to a surge in complexity.
As the scaling of transistors slows down, the practice of binding heterogeneous chips or chips in 2.5D and 3D configurations, compressing more square millimeters of silicon into a package, has also become standard.
Ausdia CEO Sam Appleton said that this complexity poses challenges to on-chip timing. All signals passing through these huge silicon chips must arrive at the right time to achieve smooth and reliable operation. He said, "These chips (even the chips inside the chips) are breaking through the reticle limit, which means their physical size is as large as the size that the foundry can manufacture. Therefore, one of the challenges we face is how to verify the timing of these giant chips and ensure that we don't miss anything."
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Most of the main players in Electronic Design Automation (EDA) software are producing more advanced timing convergence tools, which determine the clock frequency of a chip while meeting the design timing constraints.
But even with the latest EDA software, capturing the complexity of the latest and largest AI chips can also be tricky. According to Appleton, Ausdia is working to help companies understand all of this. The company's software tools can transform the building blocks of SoC into more compact abstract models without losing any timing constraints, so that other EDA tools can evaluate the timing within the entire chip at the same time.
Ausdia is trying to stay one step ahead in the challenges brought by these giant chips by utilizing its HyperBlock technology, which was released before the Design Automation Conference (DAC) held in San Francisco, California recently.Why Time is Crucial for High-Performance AI Chips
Appleton said that the increasing complexity of chips makes timing convergence more challenging.
In the latest SoCs, transistors are arranged into tens of millions to hundreds of billions of logic gates, which are bundled into up to several billion sub-blocks or "standard cells." These sub-blocks must be placed and wired together in the device's layout planning to create CPU cores, AI engines, or other IP building blocks. Ensuring that all signals passing through the chip remain on time is crucial, as any signal arriving too early or too late can disrupt the smooth operation of the device.
"If you open one of these blocks, there may be millions of cells inside, which are layout and wiring instances," said Appleton. "You put smaller blocks into larger blocks, which may contain a hundred million instances, and then assemble these larger blocks into the final chip. So, if you flatten the chip, you will have about a billion small blocks that can be placed, moved, and wired and connected to each other."
Many large AI SoCs are based on more advanced process nodes, which makes transistors have less leakage and faster clock speeds. However, timing delays are mainly determined by interconnect lines and metal wire resistance. This can lead to challenges in placing IP in the design to prevent longer interconnect delays and reduce routing congestion. For example, if you decide to increase the distance between a pair of IP blocks, you may have to add pipelines between them to ensure they remain on time.
Timing issues can affect the performance of the chip and increase various risks, from overheating to failure. However, addressing these issues may require sacrificing the device's power efficiency and area.
The timing inside the chip may be affected by many factors, such as voltage (IR) drop, temperature, and even subtle changes in the structure of transistors, which become more common in advanced process nodes.
To identify and fix timing issues in advance, most semiconductor companies use EDA tools specifically designed for static timing analysis (STA), such as Cadence Tempus and Synopsys Primetime.
As the semiconductor industry enters the era of 3D ICs, timing convergence becomes increasingly complex.
HyperBlock: Capturing the Temporal Complexity in Large AI ChipsMany leading companies in the semiconductor industry (as well as system companies trying to emulate them) possess vast data centers dedicated to designing, simulating, and verifying chip designs before they are handed over to wafer fabs. However, even the latest EDA (Electronic Design Automation) timing convergence tools struggle to directly verify a large-scale chip. Appleton points out that semiconductor engineers have devised methods to address this issue, including dividing the chip design into smaller parts for subsequent verification. But they often keep their techniques under wraps.
"Most semiconductor companies are reluctant to discuss what they do because they consider it a trade secret; we don't want anyone to know how we do it because it's a competitive advantage," says Appleton.
Ausdia's Timevision technology does not adopt a divide-and-conquer approach but instead transforms chip designs into compact code blocks that capture all their complexities. By inputting it into other EDA tools, you can run the entire chip to check for timing issues. "We are one of the industry leaders in verifying ultra-large chip designs, and we often deal with over a billion standard cells," Appleton states. "But even we encounter capacity issues."
Ausdia is attempting to address this problem with its HyperBlock technology, which can intelligently verify the largest and most advanced AI chips designed by semiconductor companies and even many system companies. The company claims that it reduces the memory required to verify whether they meet timing constraints by tenfold while increasing performance by 20 times. Appleton notes, "We want to be able to load these large designs, but we also want to do it economically."
Ausdia says that HyperBlock can be used at different stages of the design process, even before the chip functions are scheduled to logic gates (synthesis) and before all components are placed and wired. According to the company, this allows customers to "shift left" and start addressing timing issues early. HyperBlock itself can be loaded into the top level of the SoC (where the core building blocks of the IC are assembled and connected), with all complexities and timing constraints preserved within the HyperBlock.
As chip designers embrace increasingly larger design scales, "these companies want to avoid risks as much as possible because the cost of these projects is just too high," Appleton says.
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